1. Field of the Invention
The present invention is related to radiation hardened integrated circuits and, more particularly, to scannable latches for radiation hardened integrated circuits.
2. Background Description
Increasingly, space-based communication systems are including Integrated Circuits (IC) made in advanced deep sub-micron Field Effect Transistor (FET) technology. Typically, these ICs are in the insulated gate silicon technology commonly referred to as complementary metal oxide semiconductor (CMOS). CMOS ICs are advantageous in that they operate at high speed and use low power, as compared to what other technologies require for comparable speed and function.
In a space-based environment, however, ionic strikes by sub-atomic cosmic particles are known to introduce circuit disturbances. These disturbances are known as Single Event Effects (SEEs) and, as Single Event Upsets (SEUs) when occurring in storage elements. Radiation hardened storage elements latches are well known and are used, effectively, to reduce or eliminate SEE in space based IC registers, latches and other storage elements. These radiation hardened storage elements can be referred to as radiation hardened latches and are designed to protect from disturbance what is stored in them in spite of any cosmic particle hits that the storage elements might sustain.
In the past, level sensitive scan design (LSSD) latches were used in spaced-based applications to reduce an integrated circuit""s SEE sensitivity. FIG. 1 is a block diagram of a conventional LSSD latch 100. The LSSD latch 100 includes a first stage 102 and a second stage 104. The first stage 102 includes a serial input SCANIN (SI) 106 clocked by a clock A0 signal 108 and a data input DATAIN (DI) 110 clocked by a clock C0 signal 112. An output 114 of the first stage 102 is the input of the second stage 104 which is clocked by a clock B0 signal 116. An output DATAOUT 118 of the second stage 104 is an output P10 of the LSSD latch 100.
Typically, LSSD latches 100 are linked together serially to form several scan chains on a chip by connecting the output DATAOUT 118 of one LSSD latch 100 (in addition to its normal logic path connection) to the SCANIN input 106 of the next LSSD latch 100 in the chain. The IC logic is designed such that logic functions are bounded by scan chains. Thus, test data may be scanned in on one scan chain, at the input to the particular logic function and the logic function""s response to the test data may be scanned out on another chain at the logic function""s output. The data scanned out may be compared against an expected result and analyzed to determine if and where logic errors exist in the function.
During normal operation, the C0 and B0 clock signals 112 and 116 are non-overlapping phases derived from the same system clock. During each clock cycle, data at data input DATAIN 110 is latched in the first stage 102 when the C0 clock signal 112 is driven high. Then, after the first stage latch 102 has set, the C0 clock signal 112 is driven low. Next, the B0 clock signal 116 is driven high, passing the contents of the first stage 102 to the second stage 104. As the second stage is setting, the stored data passes out of the second stage on output P10 DATAOUT 118 and the second stage is set when the B0 clock signal 116 is driven low. The next clock cycle begins when the C0 clock signal 112 is again driven high.
During testing, initially, the C0 clock signal 112 is held low for all latches 100. Data is scanned in serially on the scan input SCANIN 106 by driving the A0 clock signal 108 (for one or more scan chains) with the B0 clock signal 116 until the entire test pattern has been scanned into the chain. Typically, test data is loaded into all of the scan chains, either individually or, several at a time. Once the test pattern has been scanned into each selected input test chain and the stored test pattern data has had time to pass through the function, the C0 clock signal 112 is pulsed with a single pulse to clock the function output into first stage 102 of all of the LSSD latches 100. The single pulse of C0 clock signal 112 is followed by a pulse on the B0 clock signal 116 to pass the function results to the second stage 104 of the LSSD latches. Then, the results are scanned out of the scan chains, driving individual scan chain A0 clock signal 108 with the B0 clock signal 116. Thus, individual logic functions can be tested, extensively, providing a high degree of functional certainty.
Unfortunately, modern electronic computer automated design (ECAD) tools, which are directed more to automated test pattern generation (ATPG), are incompatible with LSSD. These modern ECAD tools are incapable of using the multiple clock signals (A0, B0 and C0) 108, 116, and 112 that LSSD latches 100 require. Instead, these modem ECAD tools are adapted for logic circuits implemented using edge-triggered latches.
Edge-triggered latches set on the falling or rising edge of a single clock. For example, FIG. 2 illustrates a conventional scan d-flip-flop (scan dff) 200. The scan d flip-flop 200 includes a 2:1 multiplexer 202, which is coupled to a first level sensitive latch 204. The first level sensitive latch 204 is coupled to a second level sensitive latch 206. The scan dff 200 is clocked by a clock signal 207. The clock signal 207 is split into complementary signals by inverting clock signal 207 with inverter 208. The complementary clock signals are provided to first level sensitive latch 204 and second level sensitive latch 206, gating first and second pairs of pass gates 210, 212 and 214, 216, respectively.
When selected by select signal 218, the DATAIN 210 input passes through the 2:1 multiplexer 202 to the first pair of pass gates 210, 212 as complementary outputs 220, 222. When the clock signal 207 is low, pass gates 210, 212, are turned on so that data on complementary outputs 220, 222 are passed to first level sensitive latch 204 and, tentatively, are stored therein. With the clock signal 207 low, the second pair of pass gates 214, 216 are contemporaneously turned off, and isolate the second level sensitive latch 206 from the outputs 224, 226 of the first level sensitive latch 204.
The rising edge of clock signal 207 turns on the second pair of pass gates 214, 216 as the output of inverter 208 falls, simultaneously, to turn off the first pair of pass gates 210, 212. When the first pair of pass gates 210, 212 are turned off, the complementary outputs 220, 222 are isolated from the first level sensitive latch 204 and, so, data is latched in the first level sensitive latch 204. When the second pair of pass gates 214, 216 are turned on, outputs 224, 226 of the first level sensitive latch 204 are passed to the second-level sensitive latch 206. The state of outputs 224, 226 is stored, tentatively, in the second level sensitive latch 206 and, simultaneously, is passed out on an output DATAOUT 118. When clock signal 207 falls, on the next clock cycle, the second pair of pass gates 214, 216 are turned off, isolating the second level sensitive latch 206 from the first level sensitive latch 204, latching data in the second level sensitive latch 206 to complete the clock cycle.
Normally, when the clock signal 207 is well behaved with regularly spaced high and low periods, it is sufficient that data provided to the input DATAIN 110 meet setup (i.e., be valid for a specified period prior to the rise of clock signal 207) and hold (i.e., remain valid for a specified period after the rise of clock signal 207) timing requirements. At any other time, other than when clock signal 207 is rising, the state of DATAIN input signal 110 is specified as a xe2x80x9cdon""t carexe2x80x9d condition.
Unfortunately, an upsetting event occurring in the clock tree prior to clock signal 207 can cause a false clock pulse on clock signal 207. Since input DATAIN 110 is specified as a xe2x80x9cdon""t care,xe2x80x9d a falling edge of a false clock pulse could cause the first level sensitive latch 204 to switch states, inadvertently storing data. Further, when the input clock returns high, that invalid level is passed to the second level sensitive latch 206 and out of the scan dff 200 on output DATAOUT 118. The false clock pulse is a pulse perturbated by an SEE.
Additionally, this scan dff 200 is both incompatible with LSSD and is even more sensitive to SEE than LSSD latches. This increased sensitivity is because either the first level sensitive latch 204 or the second level sensitive latch 206 is always being gated actively. An event occurring at, or before, inverter 208 can clock the entire flip flop 200 or the second level sensitive latch 206. Furthermore, because an event occurring in the clock tree is, most likely, reflected by errors in chip latches and registers, each clock must be hardened against SEE, which increases clock power requirements and complicates SEE hardening. As a consequence, edge triggered logic, also, is power constrained.
Thus, for reasons stated above, and for other reasons, including those stated below, and that will become apparent to those skilled in the relevant art upon reading and understanding the present specification, what is needed is a scannable edge-triggered latch that is compatible with LSSD methodology, while having reduced SEE sensitivity.
The above mentioned problems with clock generation circuits and radiation hardened storage elements and other problems which will be understood by reading and studying the following specification, are addressed by the present invention.
The present invention in an example embodiment can include a scannable flip flop for space-based level sensitive scan design (LSSD) testable, edge-trigger design for integrated circuits. A scannable register may be formed from the scannable flip flops. The scannable flip flops can be radiation hardened. Each scannable flip flops can include a 2:1 input multiplexer, a first latch and a second latch. The multiplexer can be coupled to the first latch by a pair of pass gates. The pass gates can be gated by a clock signal (C0). A second pass gate pair can couple the first latch to the second latch. A second clock signal (B0) can gate the second pass gate pair. The clock signals can be non-overlapping and can be provided by a clock splitter that splits a chip clock into two individual clock phase signals. The latch and clock splitter combination can be employed as edge-triggered logic. Representing the LSSD testable circuit as an edge-triggered D-flip flop in ECAD tools permits logic synthesis and scan string creation using D-flip flop based tools. The resulting logic can operate as edge-triggered logic and can be tested using LSSD testing techniques and patterns.
An example embodiment of the present invention includes an integrated circuit including an input multiplexer, a first latch selectively coupled to an output of the input multiplexer, a second latch selectively coupled to an output of the first latch, a first clock input signal selectively coupling the first latch to the input multiplexer output, and a second clock input signal, non-overlapping and separate from the first clock input, selectively coupling the first latch to the second latch.
In one example embodiment of the present invention the input multiplexer is a 2:1 input multiplexer.
In one example embodiment of the present invention the input multiplexer includes a scan input signal and a data input signal.
In one example embodiment of the present invention the first latch is coupled to the input multiplexer by a first pair of pass gates, the first pair of pass gates being gated by the first clock input signal.
In one example embodiment of the present invention the second latch is coupled to the first latch by a second pair of pass gates, the second pair of pass gates being gated by the second clock input signal.
In one example embodiment of the present invention the first clock input signal is coupled to a first clock input signal of at least one other flip flop for space-based integrated circuits and the second clock input signal is coupled to a second clock input signal of the at least one other flip flop.
Another example embodiment of the present invention includes an integrated circuit including at least one scannable register, the at least one scannable register including a plurality of flip flops, each of the plurality of flip flops including an input multiplexer, a first latch, a first pass gate pair selectively coupling an output of the input multiplexer to an input of the first latch, a second latch, and a second pass gate pair selectively coupling an output of the first latch to an input of the second latch, a first clock input signal selectively coupling the input of the first latch to the output of the input multiplexer, and a second clock input signal non-overlapping and separate from the first clock input, selectively coupling the output of the first latch to the input of the second latch.
In one example embodiment of the present invention the input multiplexer is a 2:1 input multiplexer.
In one example embodiment of the present invention the input multiplexer includes a scan input and a data input, the plurality of flip flops being serially coupled into a scan string, an output of a first of the plurality of flip flops of the scan string being coupled to a scan input of a next of the plurality of flip flops of the scan string.
In one example embodiment of the present invention a scan input of each remaining of the plurality of flip flops is coupled to an output of another of the plurality of flip flops.
In one example embodiment of the present invention the at least one scannable register is one or more pairs of the scannable registers, a first of each of the pairs of scannable registers providing an input to a logic circuit and a second of each of the pairs of scannable registers receiving an output of the logic circuit.
In another example embodiment of the present invention, an integrated circuit including a plurality of logic circuits providing a plurality of logic functions, a first clock input signal, a second clock input signal non-overlapping and separate from the first clock input signal, a plurality of scannable registers for storing inputs to the plurality of logic functions and outputs from the plurality of logic functions, each of the plurality of scannable registers including a plurality of latches, wherein each of the plurality of latches includes an input multiplexer selecting between a scan input and a data input, a first latch selectively coupled to an output of the input multiplexer responsive to the first clock input signal, the first latch storing a state of the output of the input multiplexer, and a second latch selectively coupled to an output of the first latch responsive to the second clock input signal, the second latch storing a state of the output of the first latch and providing a latch output responsive to the state of the output of the first latch stored in the second latch, and each of the inputs to the plurality of logic functions being one of the latch outputs from one of the plurality of scannable registers, and each of the outputs from the plurality of logic functions being an input to another of the plurality of scannable registers.
In one example embodiment of the present invention the input multiplexer is a 2:1 input multiplexer.
In one example embodiment of the present invention the input multiplexer includes a scan input and a data input, the plurality of latches being serially coupled into one or more scan strings, an output of a first of the plurality of latches of the scan string being coupled to a scan input of a next of the plurality of latches of the scan string.
In one example embodiment of the present invention a scan input of each remaining of the plurality of latches is an output of another of the plurality of latches, and wherein during a test operation test pattern, data is scanned into one of the scan strings and test result data is scanned out of a second one of the scan strings.
In one example embodiment of the present invention, the circuit further includes a clock splitter, receiving a chip clock input signal and generating the first input clock signal and the second input clock signal responsive to the chip clock.
In another example embodiment of the present invention, flip flop for edge-triggered integrated circuits, the flip flop including a 2:1 input multiplexer, a first pair of pass gates having inputs coupled to a pair of outputs of the 2:1 input multiplexer, a first latch having inputs coupled to outputs of the first pair of pass gates, a second pair of pass gates having inputs coupled to a pair of outputs of the first latch, a second latch having inputs coupled to outputs of the second pair of pass gates, a first clock input signal gating the first pair of pass gates, and a second clock input signal, gating the second pair of pass gates, wherein the first clock signal and the second clock signal are non-overlapping separate clock signals, wherein during test the flip flop can be functionally tested using LSSD testing techniques and during normal operation the flip flop can operate as an edge-triggered flip flop.
In one example embodiment of the present invention the first latch and the second latch are radiation hardened latches.
In one example embodiment of the present invention the 2:1 input multiplexer includes a scan input and a data input, the flip flop being serially coupled with additional of the flip flops into one or more scan strings, an output of a first the flip flop of each of the scan strings being coupled to a scan input of a next the flip flop of the scan string.
In one example embodiment of the present invention the scan input of each remaining of the additional of the flip flops is an output of another of the additional the flip flops, wherein during a test operation test pattern data is scanned into one of the scan strings and test result data is scanned out on a second one of the scan strings.
In one example embodiment of the present invention the flip flop, when clocked by an SEU tolerant clock splitter, can be represented as a scan d flip flop for ECAD logic synthesis.
In another example embodiment of the present invention, a method of operating an integrated circuit (IC), the IC having a test mode of operation and a functional mode of operation, the method including the steps of configuring the IC in its test mode and testing the IC using LSSD test methods, and configuring the IC in its functional mode and providing a clock to an input to the IC, wherein single event upsets occurring in clock trees on the ICs are not propagated as clock pulses to latches on the IC.
In one example embodiment of the present invention the step of configuring the IC in test mode and testing includes selecting a scan input to one or more scannable registers, scanning a plurality of test patterns into the one or more scannable registers, allowing the test patterns to propagate through logic being tested on the IC to an input to an other scannable register, latching logic test results in the other scannable register, scanning test results out of the other scannable register, and checking the test results for failures and analyzing any the failures to determine a cause for each of the failures.
In one example embodiment of the present invention for any IC determined not to contain failures, the step of configuring the IC in functional mode includes configuring the scannable registers to select a data input, providing a clock to the IC, splitting the clock into one or more pairs of complementary clocks, and providing the pairs of complementary clocks to the scannable registers, wherein the registers are clocked by the pairs of complementary clocks, a first of each the pair loading data into first level sensitive latches and the second of the each pair passing the loaded data into second level sensitive latches.
It is an advantage of the invention that space-based integrated circuit (IC) testability is improved.
It is another advantage of the present invention that SEU sensitivity of space-based ICs is reduced.
It is yet another advantage of the present invention that it provides improved space-based IC chip design compatibility with LSSD techniques.